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Renesas Electronics /R7FA6M3AH /EPTPC0 /DYRPFR

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Interpret as DYRPFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FLAG8 0 (0)FLAG9 0 (0)FLAG10 0 (0)FLAG13 0 (0)FLAG14

FLAG10=0, FLAG14=0, FLAG8=0, FLAG9=0, FLAG13=0

Description

Delay_Resp Message Flag Field Setting Register

Fields

FLAG8

alternateMasterFlag

0 (0): alternateMasterFlag is set to FALSE.

1 (1): alternateMasterFlag is set to TRUE.
FLAG9

woStepFlag

0 (0): Set this bit to 0 (FALSE).

1 (1): Setting prohibited
FLAG10

unicastFlag

0 (0): unicastFlag is set to FALSE.

1 (1): unicastFlag is set to TRUE.
FLAG13

PTP profile Specific 1

0 (0): PTP profile Specific 1 is set to FALSE.

1 (1): PTP profile Specific 1 is set to TRUE.
FLAG14

PTP profile Specific 2

0 (0): PTP profile Specific 2 is set to FALSE.

1 (1): PTP profile Specific 2 is set to TRUE.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data